Solutions for the Competition [23-09-06]
Problem 1: Skewed Signals
The problem consisted of desgining a circuit with 1 input and 1 output, where the output should be a delayed version of the input. The delay specified was around 50-70 ns.
Solution
You had been given the datasheets of all the ICs given to you. For any of the gates, looking at page 2, in the bottom there is some parameter called "Propogation Delay Time". This time is the time which a signal takes to travel from the input to the output. Now the simplest thing is to put 2 NOT gates one after the other. This will intoduce a delay without changing the value. Looking at the propagation time for the NOT gate, we see that it is at max 15 ns, so we need atleast 4 NOT gates.
It may happen that the gate you have got may have a propagation delay time less than 10 ns, lets say 7 or 8 ns, so you need more than 6 NOT gates, but only 1 IC was given. Now you can use one of the other logic gates to introduce the delay, but you have to be careful that you have enough gates left for the next part.
Problem 2: The process of Digital Selection
In this problem, you had to design a circuit in which we have 2 data inputs (A1 and A2) and 1 select input, and 2 data outputs (Y1 and Y2). The condition is that:
- When Select = 0, the outputs are: Y1 = A1 and Y2 = A2
- When Select = 1, the outputs are: Y1 = A2 and Y2 = A1
Solution
In this question, you just have to make the truth table, observe the Input-Output relation and you'll get the circuit.
| Sel | A1 | A2 | Y1 | Y2 |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
You may get one of these relations:
- Y1 = (A1 * /SEL) + (A2 * SEL), Y2 = (A1 * SEL) + (A2 * /SEL)
- Y1 = (A1 + SEL) * (A2 + /SEL), Y2 = (A2 + SEL) * (A1 + /SEL)
Using these relations, you can easily design the circuit.
Problem 3: Which comes first?
This was a problem dealing with Sequential circuits. For this problem, the participants were given a D Flip-flop. Consider the two signals in problem 1. In them, the rising edge of one comes after that of another. You had to make a circuit which is capable of recognizing which of the input's rising edge comes earlier.
Let us call the inputs B and C. If rising edge of B comes before the rising edge of C, the output Y should be HIGH. When the rising edge of C comes before rising edge of B, then Y should be LOW. Assume that the width of the pulses is greater than the delay between them.
Solution
In the 7474 D Flip-flop, on the rising edge of the clock signal, whatever is the value at D is stored and is available at Q. The value does not change otherwise, it needs a rising edge of the clock signal.
We want to detect whether pulse B came before pulse C and output has to be HIGH. So, when the value is being loaded into the flip-flop, the D input should be HIGH. If pulse B comes after pulse C, then output should be LOW.
Thus according to the logic, we want the output to be the value of B at the point when either B or C go HIGH. So we can give (B + C) to the clock of the flip-flop and just B at the D input.
Thus the circuit for Problem 3 with inputs B,C and output Y is:
Or else you can give the C input to a NOT gate and output of that NOT to the Data input of flip-flop.